Practical application of dynamic temperature profiles to estimate the parameters of the square root model

Optimal experimental design for parameter estimation (OED/PE) is a promising method to improve parameter estimation accuracy and minimise experimental effort in the field of predictive microbiology. In this paper, the OED/PE methodology was applied on two practical examples: the growth of Bacillus cereus and Enterobacter cloacae in liquid whole egg product. Both strains were recovered from samples of a commercial product. The goal of the modelling exercise was to quantify the influence of temperature on bacterial growth. The Baranyi-model for bacterial growth combined with the Ratkowsky square root model to describe temperature dependence was used. Using this model, a temperature step profile was calculated based on the optimal D-criterion. The model was then fitted against the experimental bacterial growth curve measured under the dynamic temperature conditions. This process was repeated until the parameters could be estimated with sufficient accuracy, apparent by the model prediction errors. For B. cereus, prior information could be extracted from the literature, allowing calculating a dynamic temperature profile directly. Two-step profiles were sufficient to obtain a good estimation for the model parameters. No prior information could be found for E. cloacae. Therefore, a limited series of static experiments had to be conducted to obtain usable prior model parameters estimates. Only one dynamic experiment was then needed to achieve a good estimation.     

Modelling multivalent defects in thin film solar cells

Multivalent defects, e.g. double donors/acceptors or amphoteric defects, are important in materials used in solar cell production in general and in chalcopyrite materials in particular. We extended our thin film solar cell simulation software scaps to enable the simulation of multivalent defects with up to five different charge states; the algorithms presented are however able to simulate an arbitrary number of possible charge states. The presented solution method avoids numerical inaccuracies caused by the subtraction of two almost equal numbers.This new modelling facility is afterwards used to investigate the consequences of the multivalent character of defects for the simulation of chalcopyrite based solar cells.     

Analysis of the effect of structural defects on the fatigue strength of RFSSW joints using C‐scan scanning acoustic microscopy and SEM

Solid‐state refill friction stir spot welding (RFSSW) technology offers significant benefits in the fabrication of aluminium structures in the transport and aerospace industries. In this paper, the joining of 1.6‐mm‐thick Alclad 7075‐T6 aluminium alloy sheets is investigated. High‐cycle fatigue strength tests of single‐lap welded joints were carried out on an Instron E10000 testing machine with a limited number of cycles equal to 2 × 10⁶. The welding of overlap fatigue specimens was conducted using an RPS100 spot welder by Harms & Wende GmbH & Co KG. C‐mode scanning acoustic microscopy (C‐SAM) and scanning electron microscopy (SEM) were utilised to evaluate the joint quality and characterise the microstructure. The paper discusses the effect of the maximum load force and defects (voids, hook, kissing bond, bonding ligament, etc) associated with the material flow in the weld on the failure mechanism. Insufficient plasticisation of sheet material and mixing of the material in the weld area are crucial defects that influence the number of destructive cycles. The weld defects in the joint structure are a source of a decrease in the fatigue life compared with the fatigue life of defect‐free welds. It was also found that RFSSW joint defects can be effectively detected by the nondestructive C‐SAM method.     

Early design stage exploration of fixed-length block structured architectures

An important challenge concerning the design of future microprocessors is that current design methodologies are becoming impractical due to long simulation runs and due to the fact that chip layout considerations are not incorporated in early design stages. In this paper, we show that statistical modeling can be used to speed up the architectural simulations and is thus viable for early design stage explorations of new microarchitectures. In addition, we argue that processor layouts should be considered in early design stages in order to tackle the growing importance of interconnects in future technologies. In order to show the applicability of our methodology which combines statistical modeling and processor layout considerations in an early design stage, we have applied our method on a novel architectural paradigm, namely a fixed-length block structured architecture. A fixed-length block structured architecture is an answer to the scalability problem of current architectures. Two important factors prevent contemporary out-of-order architectures from being scalable to higher levels of parallelism in future deep-submicron technologies: the increased complexity and the growing domination of interconnect delays. In this paper, we show by using statistical modeling and processor layout considerations, that a fixed-length block structured architecture is a viable architectural paradigm for future microprocessors in future technologies thanks to the introduction of decentralization and a reduced register file pressure.     

Handling Transitive Relations in First-Order Automated Reasoning

We present a number of alternative ways of handling transitive binary relations that commonly occur in first-order problems, in particular equivalence relations, total orders, and transitive relations in general. We show how such relations can be discovered syntactically in an input theory, and how they can be expressed in alternative ways. We experimentally evaluate different such ways on problems from the TPTP, using resolution-based reasoning tools as well as instance-based tools. Our conclusions are that (1) it is beneficial to consider different treatments of binary relations as a user, and that (2) reasoning tools could benefit from using a preprocessor or even built-in support for certain types of binary relations.

     

A Scalable Architecture for MPEG-4 Wavelet Quantization

Wavelet-based image compression has been adopted in MPEG-4 for visual texture coding. All wavelet quantization schemes in MPEG-4—Single Quantization (SQ), Multiple Quantization (MQ) and Bi-level Quantization—use Embedded Zero Tree (EZT) coding followed by an adaptive arithmetic coder for the compression and quantization of a wavelet image. This paper presents the OZONE chip, a dedicated hardware coprocessor for EZT and arithmetic coding. Realized in a 0.5 m CMOS technology and operating at 32 MHz, the EZT coder is capable of processing up to 25.6 Mega pixel-bitplanes per second. This is equivalent to the lossless compression of 31.6 8-bit grayscale CIF images (352 × 288) per second. The adaptive arithmetic coder processes up to 10 Mbit per second. The combination of the performance of the EZT coder and the arithmetic coder allows the OZONE to perform visual-lossless compression of more than 30 CIF images per second. Due to its novel and scalable architecture, parallel operation of multiple OZONEs is supported. The OZONE functionality is demonstrated on a PC-based compression system.     

Efficient task scheduling for runtime reconfigurable systems

Recent research indicates the promising performance of employing reconfigurable systems to accelerate multimedia and communication applications. Nonetheless, they are yet to be widely adopted. One reason is the lack of efficient operating system support for these platforms. In this paper, we address the problem of runtime task scheduling as a main part of the operating systems. To do so, a new task replacement parameter, called Time-Improvement, is proposed for compiler assisted scheduling algorithms. In contrast with most related approach, we validate our approach using real application workload obtained from an application for multimedia test remotely taken by students. The proposed online task scheduling algorithm outperforms previous algorithms and accelerates task execution from 4% up to 20%.     

A generalized multiple layer data envelopment analysis model for hierarchical structure assessment: A case study in road safety performance evaluation

Data envelopment analysis (DEA) is a powerful analytical research tool for measuring the relative efficiency of a homogeneous set of decision making units (DMUs) by obtaining empirical estimates of relations between multiple inputs and multiple outputs related to the DMUs. To further embody multilayer hierarchical structures of these inputs and outputs in the DEA framework, which are prevalent in today’s performance evaluation activities, we propose a generalized multiple layer DEA (MLDEA) model. Starting from the input-oriented CCR model, we elaborate the mathematical deduction process of the MLDEA model, formulate the weights in each layer of the hierarchy, and indicate different types of possible weight restrictions. Meanwhile, its linear transformation is realized and further extended to the BCC form. To demonstrate the proposed MLDEA model, a case study in evaluating the road safety performance of a set of 19 European countries is carried out. By using 13 hierarchical safety performance indicators in terms of road user behavior (e.g., inappropriate or excessive speed) as the model’s input and 4 layered road safety final outcomes (e.g., road fatalities) as the output, we compute the most optimal road safety efficiency score for the set of European countries, and further analyze the weights assigned to each layer of the hierarchy. A comparison of the results with the ones from the one layer DEA model clearly indicates the usefulness and effectiveness of this improvement in dealing with a great number of performance evaluation activities with hierarchical structures.